1. Field of the Invention
The invention pertains generally to computer systems. In particular, it pertains to address mapping in computer systems.
2. Description of the Related Art
Computer memory is usually addressed either directly or through the use of mapping. Direct addressing involves specifying a memory address by placing the address into a register. The address contained in that register is then directly applied to the addressing bits on a memory bus. Since a register has a predetermined number of bits, the address range that can be specified in the register is limited to the range that can be specified with that number of bits. Many modern computer systems, such as system 10 of FIG. 1, use 32-bit registers and address buses, permitting them to directly address up to 4 gigabytes (GB) of memory. Since register width and memory address width are usually the same, software programs and their associated data are also generally limited to a 4 GB address space. FIG. 1 shows input-output (I/O) controller 11 with an internal 32-bit address bus for controlling transfers between the various attached devices. For simplicity, only the number of address lines are marked in the figures. As a person of ordinary skill in the art will readily recognize, the address lines will be accompanied by data lines and control lines as well. The exact number and configuration of these lines will depend on the particular bus standards being followed.
To reach more memory than is directly addressable by the contents of a register, two approaches are commonly used. In the two-stage approach, the standard address register provides some of the bits, while a separate register provides additional bits to extend the addressing range. For example, the separate register specifies one of several 4 GB blocks, while the standard 32-bit register specifies an address within that 4 GB block. Thus, a separate 4-bit register could specify one of sixteen blocks, for a total addressable space of 64 GB. Since most programs and their associated data will fit into a 4 GB memory space, the contents of the separate register do not need to be changed frequently, and the selected 4 GB block of memory can remain selected for a reasonable time. FIG. 1 shows the 4 additional address bits going from memory map 13 to memory controller 15 for a total of 36 address bits to memory 14.
Alternately, an equivalent function can be performed in the CPU, which then outputs the 36 address bits directly. In this configuration, memory map 13 or its functional equivalent is internal to CPU 12 rather than I/O controller 11.
In a similar but unrelated mapping effort, graphics controllers have conventionally provided 32-bit direct addressing of a contiguous 4 GB address space. However, the memory to be addressed is physically located in main memory, which is allocated to the graphics application in small blocks on an as-available basis. Thus the memory allocated for the graphics application at any given time, while addressed by the graphics controller as a range of contiguous virtual addresses, is actually provided as a disjointed set of smaller blocks of physical addresses, which may not even be in the same order. To correlate the virtual addresses to the physical addresses, a mapping table is provided, which translates each page (or other predetermined block size) of virtual memory into the physical page of memory allocated to it. FIG. 1 shows a graphics address redirection table (GART) 17 for translating 32-bit addresses between graphics controller 16 and memory controller 15.
Although such mapping techniques have been applied to main memory and graphics, standard I/O buses and their attached peripherals have generally not benefited from such address mapping techniques. Most standard I/O buses, such as peripheral component interconnect (PCI) bus 18, are limited to 32 or fewer address bits, and therefore cannot directly address more than 4 GB of memory. Since they frequently transfer data directly between the peripherals and main memory, this limits these transfers to the lower 4 GB of main memory, while the programs that use the data may be located in higher 4 GB sections of memory and therefore be unable to directly reach the data. The conventional approach to this problem is to transfer the data to/from the lower 4 GB memory space through bus controller 19 over the internal bus of I/O controller 11, and use software to transfer the data between the lower 4 GB and the 4 GB section of memory 14 that the application program is located in. This process is very slow and places an unreasonable burden on the processor and main memory bus, since it requires three accesses to memory rather than one: 1) write the data to a temporary buffer, 2) read the data from the temporary buffer, and 3) write the data to a permanent buffer. In a system that is already limited by memory bandwidth, this can cause an unacceptable degradation in performance.